1. Field of the Invention
The present invention relates to a zero thermal budget manufacturing process for MOS-technology power devices, such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBTs).
2. Discussion of the Related Art
MOS-technology power devices are made up of a plurality of elementary functional units connected in parallel to each conduct a fraction of the overall power device current.
Each elementary unit comprises a "body region" of one conductivity type (P type for an N-channel device), formed in a lightly doped semiconductor layer of an opposite conductivity type (N type) common to all the functional units. A heavily doped source region of the opposite conductivity type (N type) is provided inside the body region. A portion of the body region between the source region and the edge of the body region itself is covered by a thin oxide layer (the "gate oxide") and by a polysilicon layer (the "gate layer") and forms a channel region of the elementary functional unit. The source regions of the elementary functional units are contacted by a same metal layer which comprises a source electrode of the power device. Typically, the body regions have a square plan, and the power device is made up of a bidimensional array of square-plan elementary cells.
Conventionally, the body region comprises a central heavily doped region, (sometimes called the "deep body region"), and a lateral lightly doped channel region. A source region has an annular shape and is formed in the lateral channel region, substantially around the deep body region.
The source metal layer which contacts the source region also contacts the deep body region of the elementary cells to short-circuit the base-emitter junction of a parasitic bipolar junction transistor (BJT) having emitter, base and collector respectively represented by the source region, the portion of the body region under the source region, and the lightly doped semiconductor layer (an NPN transistor in the case of an N-channel power device).
A conventional manufacturing process includes: (1) epitaxially growing a lightly doped semiconductor layer of a first, e.g. N, conductivity type over a heavily doped substrate of the N conductivity type, in the case of a power MOSFET, or of the P conductivity type, in the case of an IGBT; (2) implanting, by use of a mask, and diffusing a heavy dose of a P type dopant into selected regions of the N type layer, to form the deep body regions of the elementary cells; (3) thermally growing a thin oxide layer over the surface of the N type layer; (4) depositing a polysilicon layer over the thin oxide layer; (5) selectively etching the polysilicon layer and the thin oxide layer around the deep body regions; (6) implanting a low dose of a P type dopant using the polysilicon and oxide layers as a mask; (7) diffusing the P type dopant to form channel regions extending under the thin oxide layer; and (8) implanting, by use of a mask, a heavy dose of an N type dopant into the deep body and channel regions of the cells to form annular source regions.
The doping level of the deep body regions should be suitable to obtain low-resistance contact regions for the body regions, while the doping level of the channel regions is adjusted on the basis of the threshold voltage value desired for the power device. Typical implantation doses are in the range of 10.sup.13 -10.sup.14 atoms/cm.sup.2 for the channel regions, and 10.sup.15 atoms/cm.sup.2 for the deep body regions. Three distinct masks are necessary to introduce the dopants for the various regions of the elementary cells. The windows opened in the implantation mask for the deep body regions are smaller than the windows opened by etching in the polysilicon and oxide layers to avoid lateral diffusion of the deep body regions during the thermal steps which can alter the doping profile of the channel regions. The source regions are implanted in a self-aligned way with the edges of the windows in the polysilicon and thin oxide layers, but the implantation mask must further provide unexposed surface regions in the middle of the deep body regions.
The source region may extend a significant distance into the channel region. Since the channel region has a relatively high sheet resistance (in the range of 600 ohm/square), the short-circuit of the base-emitter junction of the parasitic bipolar transistor becomes less effective with the increase in the lateral distance from the deep body region because a resistor is introduced between the emitter and the base regions of the parasitic transistor, which lowers the breakdown voltage of the power device. It would be therefore desirable to make the deep body region extend as far as possible under the source region. The problem is that, due to the lateral diffusion of the deep body region dopants during the thermal steps of the fabrication process, the dopant profile in the channel region could be altered. Thus, in conventional MOS-technology power devices, the region near the edge of the source region to the channel region of the elementary cells is critical from the point of view of the parasitic transistor triggering on.
In a commonly assigned, co-pending patent application filed on even date herewith, a manufacturing process is described which includes: (1) epitaxially growing a lightly doped semiconductor layer of a first, e.g. N, conductivity type over a heavily doped substrate of the N conductivity type, in the case of a power MOSFET, or of the P conductivity type, in the case of an IGBT; (2) thermally growing a thin oxide layer over the surface of the N type layer; (3) depositing a polysilicon layer over the thin oxide layer; (4) selectively etching the polysilicon layer and the thin oxide layer to remove them from selected portions of the N type layer surface; (5) implanting a heavy dose of a P type dopant into the selected surface portions with the polysilicon and thin oxide layers acting as a mask using an implantation energy which is sufficiently high to locate the peak dopant concentration at a prescribed distance from the surface; (6) performing a diffusion step with an amount of thermal energy large enough to cause the dopants to diffuse upwards and laterally to form heavily doped body region portions self-aligned with the edges of the polysilicon and the thin oxide layers, and lightly doped channel regions which extend laterally under the thin oxide layer; and (7) selectively implanting a heavy dose of an N type dopant to form source regions self-aligned with the polysilicon and thin oxide layers edges, and therefore substantially contained in the heavily doped body region portions.
This process not only uses one mask less than the conventional process, but also obtains source regions almost completely included in the heavily doped portion of the body regions, so that the base series resistance of the parasitic BJT is quite small along all the source region.
However, the thermal process necessary to make the dopants diffuse requires heating the device to temperatures of about 1100 C.degree. for at least 1 hour to allow the dopants to diffuse upwards and laterally, so the thickness of the gate oxide cannot be scaled down below 350-500 Angstroms. Furthermore, due to the method by which the channel region is formed (i.e., by diffusion) the channel is inevitably long (typically about 1 .mu.m). Long channels result in low conductivity and thus high "on" resistances. Also due to the lateral diffusion technique used for the formation of the channel, the dopant concentration of the channel decreases in a direction moving away from the source region, and the channel resistance increases.